Chip design

What it does

• Tracks RTL-to-GDSII progress across blocks and flags critical-path slips
• Surfaces timing, congestion, and DRC regressions the moment they appear
• Drafts the engineering update with the numbers that changed

How it works

1. 1Ingests EDA tool reports and run logs
2. 2Correlates regressions against the last clean run
3. 3Posts a ranked punch list to the design channel

Works with

• GitHub
• Jira
• Slack

Skills

• Timing-regression triage
• DRC summary